Dynamic reordering of high latency transactions using a modified micropipeline
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 336-340
- https://doi.org/10.1109/iccd.1992.276284
Abstract
An asynchronous architecture for dynamically reordering sequences of instructions issued to a processing element is presented. The optimizations supported are the exchange of two instructions and the cancellation of an instruction using its predecessor. The design is a modification of I. Sutherland's (1989) micropipeline, and is called the asynchronous reordering micropipeline (ARM). The optimizations to be effected by the ARM are captured using rewrite rules that transform instruction subsequences into more optimal (and semantically equivalent) subsequences. One application of the ARM is in optimizing transactions issued to a system called the rollback chip (RBC), which is used to accelerate the state-saving and rollback activities performed by a processing node when it runs distributed discrete-event simulation using time warp Author(s) Liebchen, A. Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA Gopalakrishnan, G.Keywords
This publication has 7 references indexed in Scilit:
- Design and evaluation of the rollback chip: special purpose hardware for Time WarpIEEE Transactions on Computers, 1992
- MicropipelinesCommunications of the ACM, 1989
- The nonuniform distribution of instruction-level and machine parallelism and its effect on performanceIEEE Transactions on Computers, 1989
- Q-modules: internally clocked delay-insensitive modulesIEEE Transactions on Computers, 1988
- Parts-R-Us.Published by Defense Technical Information Center (DTIC) ,1987
- Cache coherence protocols: evaluation using a multiprocessor simulation modelACM Transactions on Computer Systems, 1986
- Virtual timeACM Transactions on Programming Languages and Systems, 1985