Automated high-level verification against clocked algorithmic specifications
- 1 January 1993
- book chapter
- Published by Elsevier
Abstract
No abstract availableThis publication has 6 references indexed in Scilit:
- A unified framework for the formal verification of sequential circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Automated high-level verification against clocked algorithmic specificationsPublished by Elsevier ,1993
- A Method for Symbolic Verification of Synchronous CircuitsPublished by Elsevier ,1991
- Verification of Synchronous Sequential Circuits Obtained from Algorithmic SpecificationsPublished by Elsevier ,1991
- The high-level synthesis of digital systemsProceedings of the IEEE, 1990
- Sequential circuit verification using symbolic model checkingPublished by Association for Computing Machinery (ACM) ,1990