Verification of Synchronous Sequential Circuits Obtained from Algorithmic Specifications
- 1 January 1991
- book chapter
- Published by Elsevier
Abstract
No abstract availableThis publication has 28 references indexed in Scilit:
- CORAL II: linking behavior and structure in an IC design systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Area and performance optimizations in path-based schedulingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Symbolic model checking: 10/sup 20/ states and beyondPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Behavior-preserving transformations for high-level synthesisPublished by Springer Nature ,1990
- Sequential circuit verification using symbolic model checkingPublished by Association for Computing Machinery (ACM) ,1990
- Synthesis using path-based schedulingPublished by Association for Computing Machinery (ACM) ,1990
- The V compiler: automatic hardware designIEEE Design & Test of Computers, 1989
- Synthesizing circuits from behavioural descriptionsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Automatic Verification of Sequential Circuits Using Temporal LogicIEEE Transactions on Computers, 1986
- Instruction set processor specifications (ISPS): The notation and its applicationsIEEE Transactions on Computers, 1981