Test pattern generation with restrictors

Publisher Website

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/test.1993.470644

Abstract

No abstract available

Keywords

TEST PATTERN GENERATION WITH RESTRICTORS

This publication has 3 references indexed in Scilit:

Combinational profiles of sequential benchmark circuits
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
On the Acceleration of Test Generation Algorithms
IEEE Transactions on Computers, 1983
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers, 1981