Hierarchical analyzer for VLSI power supply networks based on a new reduction method
- 10 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- CREST-a current estimator for CMOS circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Techniques for calculating currents and voltages in VLSI power supply networksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- SPIDER -- A CAD System for Modeling VLSI Metallization PatternsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987