On the Three-Valued Simulation of Digital Systems
- 1 November 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-25 (11) , 1152-1156
- https://doi.org/10.1109/TC.1976.1674571
Abstract
The problem of the so-called "pessimistic" results, obtained by usingg three-valued (0,1,u) simulation for design verification of digital systems, is discussed. A complete three-valued model for the sequential portion of the digital systems is suggested. The conventional gate model is replaced by the new model, which reduces the problem considerably.Keywords
This publication has 4 references indexed in Scilit:
- A Note on Three-Valued Logic SimulationIEEE Transactions on Computers, 1972
- Hazard detection by a quinary simulation of logic devices with bounded propagation delaysPublished by Association for Computing Machinery (ACM) ,1972
- Simulation of large asynchronous logic circuits using an ambiguous gate modelPublished by Association for Computing Machinery (ACM) ,1971
- Hazard Detection in Combinational and Sequential Switching CircuitsIBM Journal of Research and Development, 1965