Network on a chip: modeling wireless networks with asynchronous VLSI

1 November 2001

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Communications Magazine

Vol. 39 (11) , 149-155
https://doi.org/10.1109/35.965373

Abstract

We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. The approach is inspired by the remarkable similarity between networks and asynchronous VLSI. Our approach results in simulators that can evaluate network scenarios much faster than real time, enabling a new class of network protocols that can dynamically change their behavior based on feedback from in situ simulation. We describe our simulation architecture, and present results that validate our approach.

Keywords

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