Hazard-non-increasing gate-level optimization algorithms
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Hazard-non-increasing optimization algorithms, optimizations on gate-level logic without introduction of any further static nor dynamic hazards, are presented. Proofs are given for general theoretical results on hazard-non-increasing transformations which serve as the basis for these algorithms. The algorithms substantially augment the set of proven hazard-non-increasing optimization techniques in the literature. These algorithms are useful for hazard-free implementations of asynchronous designs.Keywords
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