A dedicated circuit for real time motion estimation
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Presents a circuit dedicated to real-time motion estimation in video compression systems. It computes motion vectors in the range -8/+7 for 8*4n and 16*4n sized blocks at pixel rates up to 18 MHz. The architecture is based on a 128 processor systolic array. This 270000 transistor IC uses a two metal layer 1.2 mu m CMOS process.Keywords
This publication has 4 references indexed in Scilit:
- A versatile and powerful chip for real-time motion estimationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Array architectures for block matching algorithmsIEEE Transactions on Circuits and Systems, 1989
- A family of VLSI designs for the motion compensation block-matching algorithmIEEE Transactions on Circuits and Systems, 1989
- Displacement Measurement and Its Application in Interframe Image CodingIEEE Transactions on Communications, 1981