A 5-GHz Mesh Interconnect for a Teraflops Processor
Top Cited Papers
- 12 November 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro
- Vol. 27 (5) , 51-61
- https://doi.org/10.1109/mm.2007.4378783
Abstract
A multicore processor in 65-Nm technology with 80 single-precision, floatingpoint cores delivers performance in excess of a Teraflops while consuming less than 100 W. A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. The network delivers a bisection bandwidth of 2.56 Terabits per second and a per hop fall-through latency of 1 nanosecond.Keywords
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