A 4:1 time-division multiplexer IC for bit rates up to 6 Gbit/s based on a standard bipolar technology
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (5) , 785-789
- https://doi.org/10.1109/jssc.1986.1052607
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- 3.8 Gbit/s bipolar master/slave D-flip-flop IC as a basic element for high-speed optical communication systemsElectronics Letters, 1986
- Monolithic integration of a 5.3 GHz regenerative frequency divider using a standard bipolar technologyElectronics Letters, 1985
- Monolithic integrated 4:1 multiplexer and demultiplexer operating up to 4.8 Gbit/sElectronics Letters, 1985
- Integrated bipolar 4:1 time-division multiplexer for bit rates up to 3 Gbit/sElectronics Letters, 1984
- A time division multiplexer IC for bit rates up to about 2 Gbits/sIEEE Journal of Solid-State Circuits, 1984
- A simple optimisation procedure for bipolar subnanosecond ICs with low power dissipationMicroelectronics Journal, 1982
- High-speed bipolar logic circuits with low power consumption for LSI-a comparisonIEEE Journal of Solid-State Circuits, 1982
- A GaAs MSI word generator operating at 5 Gbits/s data rateIEEE Transactions on Electron Devices, 1982
- A versatile ECL multiplexer IC for the Gbit/s rangeIEEE Journal of Solid-State Circuits, 1979
- A simple but efficient analog computer for simulation of high-speed integrated circuitsIEEE Journal of Solid-State Circuits, 1977