A simple optimisation procedure for bipolar subnanosecond ICs with low power dissipation
- 31 August 1982
- journal article
- Published by Elsevier in Microelectronics Journal
- Vol. 13 (4) , 23-28
- https://doi.org/10.1016/s0026-2692(82)80005-0
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- Bipolar transistor design for optimized power-delay logic circuitsIEEE Journal of Solid-State Circuits, 1979