Logic modeling in WAVES

1 June 1990

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers

Vol. 7 (3) , 49-55
https://doi.org/10.1109/54.56467

Abstract

WAVES, which stands for waveform and vector exchange specification, is a way to represent in text the histories of logic signals and the requirements placed on them. It is intended to serve as a way of exchanging information between simulator and tester environments. A description is given of the WAVES event-value concept, which captures both the logic value sets used in simulation and the pin codes used in contemporary test-vector languages. The encoding waveforms and frames are discussed.

Keywords

LOGIC TESTING
AUTOMATIC TESTING
CIRCUIT TESTING
HISTORY
CIRCUIT SIMULATION
SIGNAL DESIGN
ENCODING
SYSTEM TESTING
MAINTENANCE ENGINEERING
COMPUTER SOCIETY

This publication has 2 references indexed in Scilit:

A VHDL standard package for logic modeling
IEEE Design & Test of Computers, 1990
The VHDL Handbook
Published by Springer Nature ,1989