Depth profile of trapped charges in oxide layer of 6H-SiC metal–oxide–semiconductor structures

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Abstract
Oxide layers etched at an angle were fabricated on a 6H‐SiC substrate by varying etching time in diluted hydrofluoric acid, and 6H‐SiC metal–oxide–semiconductor structures with various oxide thicknesses were formed. High‐frequency capacitance–voltage measurements were carried out for determining the change in gate voltages corresponding to the midgap condition as a function of the thickness of the oxide layer, and the depth profile of trapped charge density in the oxide was estimated from the result. It is found that negative charges build up near the 6H‐SiC/SiO2 interface, and that positive charges accumulate in the region at 40 nm from the interface. No significant difference is observed in the depth profiles of the trapped charge density between the oxide layers on the carbon and silicon faces. The origin of these trapped charges is discussed in conjunction with the carbon‐related compounds in the oxide layers.