Design automation of digital circuits for partially depleted SOI-technology

1 January 1996

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 108-109
https://doi.org/10.1109/soi.1996.552517

Abstract

This paper shows that it is possible to adapt commercially available layout generators to the specific needs of partially depleted (PD)-SOI-technologies with minimal area penalty. Therefore, the requirements of SOI-specific layout techniques are investigated. A design flow for automatic layout generation is proposed. An implementation is presented with a cell library created with this generator. Measurements of test circuitry at temperatures up to 390 /spl deg/C and supply voltages up to 10 V are shown.

Keywords

DESIGN AUTOMATION
DIGITAL CIRCUITS
CIRCUIT TESTING
SOFTWARE LIBRARIES
VOLTAGE
ELECTRONIC MAIL
DIGITAL SYSTEMS
CHARACTER GENERATION
TEMPERATURE
BIPOLAR TRANSISTOR CIRCUITS

This publication has 1 reference indexed in Scilit:

A methodology for converting polygon-based standards cells from bulk CMOS to SOI CMOS
International Journal of Electronics, 1997