The future of automation for high-volume Wafer fabrication and ASIC manufacturing
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE
- Vol. 74 (12) , 1775-1793
- https://doi.org/10.1109/proc.1986.13691
Abstract
Faced with increasing technical and commercial challenges from the Far East, many U.S. semiconductor manufacturers have been directing their efforts toward the Application-Specific Integrated Circuit (ASIC) or custom integrated circuit marketplace. This market is flourishing because advances in technologies such as gate arrays and standard cells now make it significantly easier to obtain system cost and performance advantages by integrating nonstandard functions on silicon. They are attractive to U.S. manufacturers because they place a premium on sophisticated design tools, familiarity with customer needs and applications, and fast turn-around fabrication. These are areas where U.S. manufacturers believe they have an advantage and, consequently, they believe they will not suffer from the severe price/manufacturing competition encountered in conventional high-volume semiconductor products. In the past, automation was often considered viable only for high-volume manufacturing, but automation becomes a necessity in the new ASIC environment. ASIC requirements for increased product variability, strict delivery schedules, and the need to guarantee acceptable yields at the individual wafer level (as opposed to yields averaged over large lots) are the areas which automation must address. These challenges, combined with the need for more efficient and contamination-free production environments, are certain to stress the resources of even the most competent companies. This paper explores some challenges which must be met before automated custom device manufacturing can be successful and outlines the role automation will play in helping to meet these challenges.Keywords
This publication has 13 references indexed in Scilit:
- CASTAM: A process variation analysis simulator for MOS LSI'sIEEE Transactions on Electron Devices, 1984
- Management's Role in Planning the Automated FactoryIEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1984
- Modeling of defects in integrated circuit photolithographic patternsIBM Journal of Research and Development, 1984
- Palladio: An exploratory environment for circuit designComputer, 1983
- FablePublished by Association for Computing Machinery (ACM) ,1983
- Statistical modeling for efficient parametric yield estimation of MOS VLSI circuitsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Future Needs For Semiconductor CharacterizationPublished by SPIE-Intl Soc Optical Eng ,1981
- The Use of Electrical Test Structure Arrays for Integrated Circuit Process EvaluationJournal of the Electrochemical Society, 1980
- A General Etching Simulator for VLSI Lithography and Etching Processes: Part II - Application to Deposition and EtchingIEEE Journal of Solid-State Circuits, 1980
- Models for computer simulation of complete IC fabrication processIEEE Transactions on Electron Devices, 1979