Semiconductor Instability Failure Mechanisms Review

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Abstract
This paper reviews the mechanisms of semiconductor instabilities for the purpose of better understanding this very complex phenomenon. As a result of this understanding, the semiconductor instabilities can be kept to a minimum in design and production. The basic ideas, diagrams, and references are presented for: instabilities due to surface charge on the silicon dioxide (SiO2), conduction on oxide surfaces/lateral charge spreading, instabilities caused by charges within the SiO2, instabilities in double-layer insulator structures, hFF degradation by avalanched emitter-base junction, and instabilities due to parasitic actions. A case study in reducing manufacturing assembly fallout is presented. Its electrical manifestations, as hFF degradation, the causes and corrective action are described. This study shows the importance of vendor-user cooperation to find the proper corrective action. Electrical diagnostic techniques such as the current-voltage curve trace characteristics of a junction are reviewed. The threshold test used in detecting parasitic MOS action caused by improper layout and/or ionic contamination is presented. They are used to pinpoint the area of instability on the semiconductor. High temperature bake and biased operating life procedures and their use in identifying and pinpointing causes of instabilities are discussed. Finally a method for removing various materials and/or layers of a semiconductor device is presented. This method is used in pinpointing the manufacturing step which might have caused the observed abnormal electrical characteristics.

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