Hysteresis cycle in the latch-up characteristic of wide CMOS structures

1 May 1988

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 9 (5) , 214-216
https://doi.org/10.1109/55.694

Abstract

Experimental results are interpreted in terms of a simple lumped-element model that is also used to reproduce the hysteresis phenomenon with discrete components. The hysteresis is related to a three-dimensional (3-D) nonuniformity in the current distribution. Such hysteresis can lead to an erroneous evaluation of latchup parameters, such as the holding current density.

Keywords

HYSTERESIS
CURRENT DISTRIBUTION
SEMICONDUCTOR DEVICE MODELING
CURRENT DENSITY
TWO DIMENSIONAL DISPLAYS
EQUIVALENT CIRCUITS
CIRCUIT TESTING
DOPING
PHYSICS
VOLTAGE

This publication has 2 references indexed in Scilit:

Three-dimensional distribution of CMOS latch-up current
IEEE Electron Device Letters, 1987
Three-dimensional effects in CMOS latch-up
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1986