Evolutionary fault recovery in a Virtex FPGA using a representation that incorporates routing
- 22 March 2004
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Evolved fault tolerance in evolvable hardwarePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Fault grading FPGA interconnect test configurationsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A comparison of dynamic fitness schedules for evolutionary design of amplifiersPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- GeneticFPGA: evolving stable circuits on mainstream FPGA devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Bridging the genotype-phenotype mapping for digital FPGAsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Evolving messy gates for fault tolerance: some preliminary findingsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- On the use of distributed reconfigurable hardware in launch control avionicsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fault-tolerant evolvable hardware using field-programmable transistor arraysIEEE Transactions on Reliability, 2000
- A high-performance computing module for a low earth orbit satellite using reconfigurable logicPublished by Springer Nature ,1998