Layout and bias considerations for preventing transiently triggered latchup in CMOS
- 1 March 1984
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 31 (3) , 315-321
- https://doi.org/10.1109/t-ed.1984.21522
Abstract
This paper investigates several techniques for hardening CMOS curcuitry against transiently triggered latchup. Measurements of critical rise time are made on four variations of the p-n-p-n structure inherent to CMOS. For each structure the n-well and substrate shunt resistances are varied as is the substrate bias. These measurements are performed on both bulk and epi-samples using both topside and backside substrate contacts. Comparison of the parasitic bipolar transistors comprising the p-n-p-n structures reveals that differences in bipolar behavior do not completely explain the differences in p-n-p-n latchup behavior. Test results are used to rate the various hardening techniques.Keywords
This publication has 3 references indexed in Scilit:
- A transient analysis of latchup in bulk CMOSIEEE Transactions on Electron Devices, 1983
- Latch-Up Control in CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1979
- Latch-Up in CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1973