A transient analysis of latchup in bulk CMOS
- 1 February 1983
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 30 (2) , 170-179
- https://doi.org/10.1109/t-ed.1983.21091
Abstract
This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.Keywords
This publication has 3 references indexed in Scilit:
- A model for the parasitic SCR in bulk CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1980
- Latch-Up Elimination in Bulk CMOS LSI CircuitsIEEE Transactions on Nuclear Science, 1980
- Latch-Up Control in CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1979