On Monte Carlo Testing of Logic Tree Networks
- 1 June 1976
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-25 (6) , 664-667
- https://doi.org/10.1109/tc.1976.1674670
Abstract
It is shown that by a proper selection of the probabilities of 0 and 1 at the inputs, the efficiency of random test generation can be improved. This correspondence includes some results describing the testing of actual logic networks used in a computer.Keywords
This publication has 6 references indexed in Scilit:
- Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic NetworksIEEE Transactions on Computers, 1975
- Probabilistic Treatment of General Combinational NetworksIEEE Transactions on Computers, 1975
- An Advanced Fault Isolation System for Digital LogicIEEE Transactions on Computers, 1975
- Analysis of Logic Circuits with Faults Using Input Signal ProbabilitiesIEEE Transactions on Computers, 1975
- Analysis of the detectability of faults by random test patterns in a special class of NAND networksComputers and Electrical Engineering, 1973
- An Automatic Test Generation System for Illiac IV Logic BoardsIEEE Transactions on Computers, 1972