Organization of Semiconductor Memories for Parallel-Pipelined Processors

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Abstract
An organization of interleaved multimodule semiconductor memories is studied to facilitate accessing of memory words by a parallel-pipelined processor. All modules are assumed to be identical and to have address cycle (address hold time) and memory cycle of a and c segment time units, respectively. A total of N(=2n) memory modules are arranged such that there are l(=2b) lines for addresses and m(=2n-b) memory modules per line. For a parallel-pipelined processor of order (s,p) which consists of P parallel processors each of which has s degrees of multiprogramming, there can be up to s · p memory requests in each instruction cycle. Memory request collisions are bound to occur in such a system. Performance is evaluated as a function of the memory configuration. Results show that for reasonably large values of N, high performance can be obtained even in the nonbuffered case when l is a · p or more. Buffering has maximum effect on performance when l is near a · p. When l must be grater than a · p for adequate performance in the nonbuffered case, buffering can be used to reduce l while maintaining performance.

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