Self-assembled near-zero-thickness molecular layers as diffusion barriers for Cu metallization

Devising ultrathin barrier layers to prevent Cu diffusion into ${\mathrm{SiO}}_{\mathrm{2}}\mathrm{-based}$ dielectrics is a major challenge that must be met to increase the speed, number density, and performance of microelectronics devices. Here, we demonstrate the use of near-zero-thickness (<2-nm-thick) self-assembled molecular monolayers (SAMs) as candidates for this application. ${\mathrm{Cu/SiO}}_{\mathrm{2}}\mathrm{/Si}\text{(001)}$ metal–oxide–semiconductor capacitors, with and without SAMs at the ${\mathrm{Cu/SiO}}_{\mathrm{2}}$ interface, were annealed at 200 °C in a 2 MV cm⁻¹ electrical field. Capacitance–voltage and current–voltage measurements of SAM-coated capacitors indicate that SAMs with aromatic terminal groups inhibit Cu diffusion into ${\mathrm{SiO}}_{\mathrm{2}}.$ They consistently show more than four-orders-of-magnitude lower leakage currents and a factor-of-4 higher time to failure when compared with the corresponding values from samples without SAMs at the interface. SAMs with short tail lengths or aliphatic terminal groups are ineffective in hindering Cu diffusion, indicating that the molecular length and chemical configuration are key factors determining the efficacy of SAMs as barriers. We propose that the steric hindrance offered by the terminal groups in the SAMs are responsible for the barrier properties.