Characterization of a thin Si-implanted and rapid thermal annealed n-GaAs layer

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Abstract
Very thin, high carrier concentration layers for high performance GaAs field‐effect transistors are realized by lamp annealing, combined with low‐energy (<30 keV) ion implantation. The characteristics of these thin layers are investigated by the Hall effect, capacitance‐voltage, photoluminescence, and secondary ion mass spectrometry (SIMS). The optimum temperature giving the maximum sheet carrier concentration is the result of a balance between damage recovery and acceptor generation. The optimum temperature decreases as the implantation energy is reduced. The effective implanted layer thicknesses obtained by SIMS are larger than the Lindhard–Scharff–Schiott calculated values. The minimum effective active layer thickness of 0.045 μm is obtained with a 10‐keV implanted sample. This value is about one‐half that obtained for the 30‐keV implanted furnace annealed sample.