From massively parallel image processors to fault-tolerant nanocomputers

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Abstract
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regular structures and mainly local interconnections, SIMD or SIMD-like architectures have been proposed for a large-scale integration of recently developed quantum and nanoelectronic devices. In this paper, we present a fault-tolerant technique suitable for an implementation in nanoelectronics, the triplicated interwoven redundancy (TIR). The TIR is a general class of triple modular redundancy (TMR), but implemented with random interconnections. A prototype structure for an image processor is proposed for the implementation of the TIR technique and a simulation based reliability model is used to investigate its fault-tolerance. The TIR is extended to higher orders, namely, the N-tuple interwoven redundancy (NIR), to achieve higher system reliabilities. It is shown that the reliability of a general TIR circuit is, in most cases, comparable with that of an equivalent TMR circuit, and that the design and implementation of restorative devices (voters) are important for the NIR (TIR) structure. Our study indicates that the NIR (TIR) is in particular suitable for an implementation by the manufacturing process of stochastically molecular assembly, and that it may be an effective fault-tolerant technique for a massively parallel architecture based on molecular or nanoelectronic devices.