A circuit technology for high-speed battery-operated 16-Mb CMOS DRAM's
- 1 January 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 28 (11) , 1084-1091
- https://doi.org/10.1109/4.245586
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- A 20 ns battery-operated 16 Mb CMOS DRAMPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A high-speed sensing scheme for 1T dynamic RAMs utilizing the clamped bit-line sense amplifierIEEE Journal of Solid-State Circuits, 1992
- A 64-Mb DRAM with meshed power lineIEEE Journal of Solid-State Circuits, 1991
- An experimental 1.5-V 64-Mb DRAMIEEE Journal of Solid-State Circuits, 1991
- A circuit design to suppress asymmetrical characteristics in high-density DRAM sense amplifiersIEEE Journal of Solid-State Circuits, 1990
- A 1.5-V DRAM for battery-based applicationsIEEE Journal of Solid-State Circuits, 1989