A High-performance Ultra-thin Quarter-Micron CMOS/SIMOX Technology

1 January 1993

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 25-26
https://doi.org/10.1109/vlsit.1993.760227

Abstract

We desc r ibe a high-performance 0.25-/spl mu/m-gate CMOS/SIMON technology, and high-speed CMOS circuit operation at a low power supply voltage of 1-2 V. Fully-depleted N/sup +/ poly-Si gate nMOSFETs and P/sup +/ poly-St gate pKOSFETs with 7-nm-thick gate oxide were fabricat- ed using planarized sub-quarter-micron Isolation and a two-level metallization technique. The propagation delay time of a CMOS ring oscillator is 30 ps/stage at the supply voltage of 2 V and 45 ps/stage at 1 V.

Keywords

LOGIC GATES
MOS DEVICES
CMOS INTEGRATED CIRCUITS
ION IMPLANTATION
FABRICATION
IMPLANTS
CMOS TECHNOLOGY

This publication has 2 references indexed in Scilit:

Practical reduction of dislocation density in SIMOX wafers
Electronics Letters, 1990
A New Self‐Aligned Planar Oxidation Technology
Journal of the Electrochemical Society, 1987