High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits

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Abstract
New high-performance building blocks for two-phase micropipelines are presented, and pseudo-static Svensson-style double edge-triggered D-flip-flops (DETDFF) for datapath storage are developed in place of traditional capture-pass or transmission gate latches. A DETDFF FIFO buffer implementation is compared with the current state-of-the-art micropipeline implementation using four-phase controllers designed by Day and Woods for the AMULET-2 processor and also with Sutherland's original two-phase micropipeline. All three designs were simulated in the MOSIS 1.2 µm CMOS process under the worst-case process corner with a 4.6 V power supply and at 100°C. The authors' SPICE simulations show that the DETDFF design has 70% and 150% higher throughput than Day and Woods' and Sutherland's, respectively. This higher throughput is due to latching the data on both edges of the latch control, removing the need for a reset phase and simplifying the control structures. In addition, two commonly used micropipeline event-control structures, the select and toggle elements, are implemented using the extended-burst-mode 3D synthesis system. Detailed simulations demonstrate that our implementations are up to 50% faster than traditional implementations. This speed advantage can be primarily attributed to careful applications of generalised C-elements rather than discrete basic gates.

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