Hierarchical Circuit Extraction with Detailed Parasitic Capacitance
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 337-345
- https://doi.org/10.1109/dac.1983.1585671
Abstract
This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout and then compares this netlist to a reference circuit netlist obtained from a schematic. The circuit extraction phase of IV is described in detail. A unique characteristic of the program is the treatment of parasitic capacitance. IV is currently being used in a production environment to extract circuits in a variety of NMOS and CMOS processes.Keywords
This publication has 1 reference indexed in Scilit:
- Circuit Recognition and Verification Based on Layout InformationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981