Circuit Recognition and Verification Based on Layout Information
- 1 January 1981
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 684-689
- https://doi.org/10.1109/dac.1981.1585427
Abstract
The mathematical and technical background information for our highly efficient procedure of circuit recognition and verification from layout information is presented. Complete verification and extremely short computing times are the main goals. This procedure can be performed for bipolar as well as for MOS technologies and is part of the whole layout-control system LOCATE.Keywords
This publication has 5 references indexed in Scilit:
- Fast algorithm for LSI artwork analysisPublished by Association for Computing Machinery (ACM) ,1988
- Unified Shapes Checker - A Checking Tool for LSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Circuit Simulation and Timing Verification based on MOS/LSI Mask InformationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1979
- Network recognition of an MOS integrated circuit from the topography of its masksComputer-Aided Design, 1978
- Theory of multiplace graphsIEEE Transactions on Circuits and Systems, 1975