Stability Analysis of an Nth Power Digital Phase-Locked Loop - Part I: First-Order DPLL

1 August 1980

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Communications

Vol. 28 (8) , 1343-1354
https://doi.org/10.1109/tcom.1980.1094771

Abstract

The behavior of a digital phase-locked loop (DPLL) which tracks the positive-going zero crossings of the incoming signal can be characterized by a nonlinear difference equation in the phaseerror process. This equation was first presented by Gill and Gupta for the CW loop, and modified by Osborne and Lindsey for theNth power loop. Stability results have been previously obtained for first- and second-order loops by linearizing the equation about the steady-state solution. However, in this paper, a mathematically more rigorous and powerful approach is introduced whereby the acquisition behavior is studied by formulating the equation as a fixed-point problem. Stability results can be obtained by studying the nonlinear equation directly, using theorems pertaining to the convergence behavior of the Picard iterates, e.g., Ostrowski's Theorem and the Contraction Mapping Theorem. Using this formulation, we present some new stability results (and rederive some previously obtained results) for the first- and second-order DPLL's. Then, some stability results for the third-order DPLL are derived for the first time. The first-order DPLL results appear in Part I, and the higher order DPLL results appear in Part II.

Keywords

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