Fully Dynamic Switch-Level Simulation of CMOS Circuits
- 1 March 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (2) , 282-289
- https://doi.org/10.1109/tcad.1987.1270272
Abstract
A new algorithm for switch-level simulation is suggested which allows the simulator to be fully dynamic, i.e., several signals may propagate in the network simultaneously. It is shown how this algorithm can be combined with a timing model. Finally, it is demonstrated how a simulator based on this algorithm can handle problems such as charge sharing and clock skewing in general CMOS circuits.Keywords
This publication has 5 references indexed in Scilit:
- Switch-level simulation and the pass transistor EXOR gateIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- A Switch-Level Timing Verifier for Digital MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- A Switch-Level Model and Simulator for MOS Digital SystemsIEEE Transactions on Computers, 1984
- Signal Delay in RC Tree NetworksIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983
- Local Relaxation Algorithms for Event-Driven Simulation of MOS Networks Including Assignable Delay ModelingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1983