High speed regenerator-section terminatingLSI operating up to 2.5 Gbit/s using 0.5 µmSi bipolar standard-cell technology

11 May 1995

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 31 (10) , 791-792
https://doi.org/10.1049/el:19950528

Abstract

A 2.5 Gbit/s 5.6 Kgate LSI for the STM-64 regenerator-section terminator was fabricated using bipolar standard-cell technology for gigabit per second operation. The technology features high performance cell design and LSI layout design based on an accurate timing analysis. The LSI achieves twice the bit rate and half the power dissipation of reported LSIs.

Keywords

SDH PROTOCOL
STM-64 REGENERATOR-SECTION TERMINATOR
TIMING ANALYSIS
0.5 MICRON
CELL DESIGN
REGENERATOR-SECTION TERMINATING LSI
LSI LAYOUT DESIGN
BIPOLAR STANDARD-CELL TECHNOLOGY
GIGABIT PER SECOND OPERATION
POWER DISSIPATION
BIT RATE
2.5 GBIT/S

This publication has 2 references indexed in Scilit:

High-speed regenerator section terminating LSIs
Electronics Letters, 1993
Line terminating multiplexers for SDH optical networks
Journal of Lightwave Technology, 1993