Statistical Circuit Simulation Modeling of CMOS VLSI
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 5 (1) , 15-22
- https://doi.org/10.1109/tcad.1986.1270173
Abstract
This paper describes a complete modeling approach for MOS VLSI circuit design which is highly automated and provides statistically relevant parameter files. A description of key model equations, which includes the effects of nonuniformly doped channels, charge sharing bulk-charge terms, and lateral and vertical field mobility reduction terms, will be given. A methodology of parameter extraction for both physical and "fitted" terms will be described. Appropriate distributions of these parameters are then generated and checked for correlations among these parameters. A statistical modeling routine has been developed that then generates device parameter bound files from transformed independent variables. Finally, simulations performed with statistical best-worst case parameter files were compared to data for many transistors from the same lot and process.Keywords
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