A power model for routers: modeling Alpha 21364 and InfiniBand routers

This publication has 11 references indexed in Scilit:

• An alternative architecture for on-chip global interconnect: segmented bus power modeling
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Power constrained design of multiprocessor interconnection networks
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• A delay model and speculative architecture for pipelined routers
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• The Alpha 21364 network architecture
  IEEE Micro, 2002
• Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links
  IEEE Computer Architecture Letters, 2002
• Low-power system-level design of VLSI packet switching fabrics
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
• Route packets, net wires
  Published by Association for Computing Machinery (ACM) ,2001
• Addressing the system-on-a-chip interconnect woes through communication-based design
  Published by Association for Computing Machinery (ACM) ,2001
• The design and use of simplepower
  Published by Association for Computing Machinery (ACM) ,2000
• Myrinet: a gigabit-per-second local area network
  IEEE Micro, 1995