A 10 Gb/s silicon bipolar IC for PRBS testing
- 23 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The ongoing development of telecommunication circuits for the STM hierarchy is now reaching the STM 64 level(/spl sim/10 Gb/s). This creates the need for fast test circuitry. A silicon bipolar IC integrating all functions for the pseudo random binary sequence (PRBS) test of circuits and transmission systems up to 40 Gb/s is an advanced version of a previous design with limited performance. The following features are added: (1) on-chip bit error counting and PC based bit error rate evaluation and display, (2) sequence lengths switchable between 2/sup 16/-1 and 2/sup 23/-1 b (according to CCITT recommendations), (3) automatic PRBS test word synchronization of two chips for the purpose of direct external 4:1 multiplexing up to 40 Gb/s, and (4) auto-start.Keywords
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