Cost-performance evaluation of memory hierarchies

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Abstract
The stack processing method is used to compare the cost-performance ($/access) between the following: 1) two-level and three-level hierarchies; and 2) hierarchies using random access and serial access memories as a backing store. It was found that busswidth between levels in the hierarchy strongly affects the system cost-performance, and the access time ratio between the backing store and buffer somewhat less. With the technology cost assumptions used in this study, the three-level hierarchy does not have as good a figure of merit ($/access) as the two-level hierarchy unless the access time ratio exceeds about fifty. Also, random access devices are advantageous over serial access devices for backing store applications only when the memory capacity is less than 1 Mbyte. For capacities of 4 Mbyte and 16 Mbyte serial access stores with shift register lengths of 256 bit and 1024 bit, respectively, look favorable.

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