On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches
- 1 March 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 8 (3) , 268-278
- https://doi.org/10.1109/43.21846
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- A Switch-Level Timing Verifier for Digital MOS VLSIIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1985
- Timing Analysis for nMOS VLSIPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Timing Verification and the Timing Analysis programPublished by Association for Computing Machinery (ACM) ,1982
- Synchronous path analysis in MOS circuit simulatorPublished by Association for Computing Machinery (ACM) ,1982