Accelerated Fault Simulation and Fault Grading in Combinational Circuits
- 1 September 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 6 (5) , 704-712
- https://doi.org/10.1109/tcad.1987.1270316
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- RFSIM: Reduced Fault SimulatorIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Gutting chip-testing costs: Designing VLSI circuits for testability is the most efficient way to reduce the relative costs of assuring high chip reliabilityIEEE Spectrum, 1985
- STAFAN: An Alternative to Fault SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- Critical Path Tracing - An Alternative to Fault SimulationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Diagnosis & Reliable Design of Digital SystemsPublished by Springer Nature ,1976
- A Deductive Method for Simulating Faults in Logic CircuitsIEEE Transactions on Computers, 1972