An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMS
- 1 January 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 33 (7) , 1730-1733
- https://doi.org/10.1109/TNS.1986.4334679
Abstract
A technique that will improve RAM cell performance while maintaining single event upset immunity has been identified. The resistor-hardening configuration combines cross-coupled gate resistors and a pair of resistors used to isolate the miore sensitive devices (those not fabricated in wells). Improvements in RAM cell write time and critical charge are discussed as well as the impact of this technique on the cell's noise miargin.Keywords
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