A new BIST approach for delay fault testing
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 284-288
- https://doi.org/10.1109/edtc.1994.326863
Abstract
A new built-in self testing (BIST) method for the detection of delay faults is proposed. It is shown that all possible pattern pairs can be generated with a MISR using all input combinations. In order to reduce the test pattern set, deterministic delay test generation is used and a minimal set of input vectors is derived via clique covering. Experimental results show that by just using the all-0 and all-1 input vectors, the non-robust path delay fault coverage ranges from 85% to 100%.<>Keywords
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