A self-testing ROM device

1 January 1981

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXIV, 176-177
https://doi.org/10.1109/isscc.1981.1156147

Abstract

A self-testing 1Kb ROM affording in the test mode functional conversion of peripheral subcircuits into test aids on the chip will be reported. Error coverage is better than 99.6% and area overhead is 15%.

Keywords

BUILT-IN SELF-TEST
READ ONLY MEMORY
AUTOMATIC TESTING
CIRCUIT TESTING
COUNTING CIRCUITS
MICROPROCESSORS
LATCHES
SWITCHES
PRODUCTION
TEST PATTERN GENERATORS

This publication has 1 reference indexed in Scilit:

Built-in test for complex digital integrated circuits
IEEE Journal of Solid-State Circuits, 1980