A 256K ROM fabricated using n-well CMOS process technology
- 1 August 1982
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 17 (4) , 723-726
- https://doi.org/10.1109/JSSC.1982.1051802
Abstract
A 256K bit CMOS ROM with a speed-power product of 0.085 pJ/bit has been developed. The excellent speed-power product and the high packing density have been achieved by using n-well CMOS technology and a serial-parallel ROM cell structure. The concept and characteristics of a serial-parallel ROM cell structure are discussed and compared to conventional ROM cell structures. The serial-parallel ROM cell structure gives more flexibility for ROM matrix design. The chip size and memory cell size of the 256K CMOS ROM are 5.98/spl times/6.00 mm and 7.0/spl times/7.0 /spl mu/m, respectively. Access time is 370 ns. The power supply currents in active and quiescent modes are 12 mA and less than 0.1 /spl mu/A at +5 V, respectively.Keywords
This publication has 1 reference indexed in Scilit:
- Minimum size ROM structure compatible with silicon-gate E/D MOS LSIIEEE Journal of Solid-State Circuits, 1976