An integer linear programming based approach for parallelizing applications in on-chip multiprocessors
- 1 January 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 703-708
- https://doi.org/10.1109/dac.2002.1012715
Abstract
With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under energy and performance constraints.Keywords
This publication has 7 references indexed in Scilit:
- Power and energy reduction via pipeline balancingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Energy-driven integrated hardware-software optimizations using SimplePowerACM SIGARCH Computer Architecture News, 2000
- System-level power consumption modeling and tradeoff analysis techniques for superscalar processor designIEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
- Profile-driven code execution for low power dissipationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2000
- A chip-multiprocessor architecture with speculative multithreadingIEEE Transactions on Computers, 1999
- The case for a single-chip multiprocessorPublished by Association for Computing Machinery (ACM) ,1996
- CACTI: an enhanced cache access and cycle time modelIEEE Journal of Solid-State Circuits, 1996