An efficient pipelined dataflow processor architecture

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Abstract
This paper demonstrates that the principles of pipelined instruction execution can be effectively applied in dataflow computers, yielding an architecture that avoids the main sources of pipeline gaps during program execution in many conventional processor designs. The new processing element design uses an architecture called argument-fetch dataflow architecture. It has two parts: a dataflow instruction scheduling unit (DISU) and a pipelined instruction processing unit (PIPU). The PIPU is an instruction processor that uses many conventional techniques to achieve fast pipelined operation. The DISU holds the dataflow signal graph of the collection of dataflow instructions allocated to the processing element, and maintains a large pool of enabled instructions available for execution by the PIPU. The new architecture provides a basis for achieving high performance for many scientific applications. To show that the realization of an efficient dataflow processing element is feasible, a trial design and fabrication of an enable memory-a key component of the DISU-is reported.

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