Josephson 4 K-bit cache memory design for a prototype signal processor. I. General overview

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Abstract
This paper presents an overview of the status of a Josephson cache chip design at IBM in the Fall of 1983. Details of the design, organized as 1 K×4 bits, and employing a 2.5‐μm niobium edge‐junction technology, are found in the subsequent two adjoining papers. This paper presents, in a broader perspective than the adjoining papers, the background, motivation, changes from previous designs, and general difficulties of the design. General considerations related to the fabrication process and design methodology and an overview of components and the system environment are presented. A Pb‐predecessor design is used as a point of reference; the discussions emphasize changes to that work. Finally, inherent design difficulties and remaining uncertainties are discussed.

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