Optimization of field-programmable gate array logic block architecture for speed

9 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 6.1/1-6.1/6
https://doi.org/10.1109/cicc.1991.164141

Abstract

The authors explore the effect of the choice of logic block on the speed of a field-programmable gate array (FPGA). A set of logic circuits was implemented as FPGAs, each using a different logic block, and the speed of the implementation was measured. While the result depends on the delay of programmable routing, experiments indicate that wide input PLA (programmable logic array)-style AND-OR gates, four- and five-input lookup tables, and certain multiplexer configurations produce the lowest total delay over the important values of routing delay. Furthermore, significant gains in performance (from 10% to 41% reduction in total delay) can be achieved by connecting a small number of logic blocks together using hard-wired connections.<>

Keywords

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