A 23-ns 256 K EPROM with double-layer metal and address transition detection
- 1 October 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (5) , 1250-1258
- https://doi.org/10.1109/jssc.1989.572589
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- A 7.5-ns 32 K*8 CMOS SRAMIEEE Journal of Solid-State Circuits, 1988
- A 35-ns 128K×8 CMOS SRAMIEEE Journal of Solid-State Circuits, 1987
- A 21-ns 32 K×8 CMOS static RAM with a selectively pumped p-well arrayIEEE Journal of Solid-State Circuits, 1987