A 21-ns 32 K×8 CMOS static RAM with a selectively pumped p-well array
- 1 October 1987
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 22 (5) , 704-711
- https://doi.org/10.1109/jssc.1987.1052803
Abstract
No abstract availableThis publication has 8 references indexed in Scilit:
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- A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A selectively pumped p-well memory array technology for high density static RAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1986
- A 10-/spl mu/W standby power 256K CMOS SRAMIEEE Journal of Solid-State Circuits, 1985
- A 45-ns 256K CMOS static RAM with a tri-level word lineIEEE Journal of Solid-State Circuits, 1985
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- Ion-implanted thin polycrystalline-silicon high-value resistors for high-density poly-load static RAM applicationsIEEE Transactions on Electron Devices, 1985
- A low power 46 ns 256 kbit CMOS static RAM with dynamic double word lineIEEE Journal of Solid-State Circuits, 1984